The present invention relates generally to the field of reconfigurable devices. Reconfigurable devices, such as programmable logic devices (PLDs), are used to implement a desired circuit design. A PLD is typically composed of a number of functional blocks that use either a combination of logic gates or look-up tables to implement a general-purpose logic operation. The logic operation of each functional block can be defined to implement a portion of the desired circuit design. The functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively establishes connections between the functional blocks, enabling the PLD to perform the functions of the desired circuit design. The configurable switching circuit also establishes connections between some of the functional blocks and the pins of the PLD, so that data can be input to and output from the PLD. Configuration information determines the function of the configurable switching circuit and the functional blocks. The configuration information may be loaded into the PLD or other reconfigurable device from a separate configuration device.
In addition to functional blocks adapted to implement a variety of general-purpose logic operations, reconfigurable devices can include specialized components used to implement specific functions. These specialized components, referred to as intellectual property or IP cores, are specifically adapted to their intended functions. Example IP cores include memory devices, signal processing devices, phase-locked loop devices, and high-speed serial communication devices, which can be used to implement a variety of serial communication standards, such as SerialLite, Ethernet and Gigabit Ethernet, Fibrechannel, PCI-X, and Infiniband. A reconfigurable device may include several IP cores, each used to perform a different specialized function.
Testing reconfigurable devices having both general functional blocks and specialized IP cores presents numerous challenges. Both the functional blocks and the IP cores need to be tested. In addition, the connections interfacing the IP cores and the other portions of the reconfigurable device, for example function blocks, also need to be tested. To test the interface between the IP cores and functional blocks, one prior approach uses a set of functional test data to test the operation of the IP core for all possible input and output signals. However, this functional testing requires manual creation of the entire set of test data by engineers with detailed understanding of the operation of the IP core. This introduces the possibility of creating faulty test data. Additionally, small modifications to the IP core require a new set of test data to be created. Furthermore, complex IP cores may have hundreds of interface connections, making the manual creation of test data a difficult and time-consuming process.
Another prior approach to testing interface connections between hard-wired IP and functional blocks of a reconfigurable device includes a set of boundary scan registers on the reconfigurable device to input test data to the IP core and to capture outputs from the IP core. The test data for the interface connections between the boundary scan registers and the IP core can be created using automated test program generation (ATPG) software, greatly simplifying the creation of test data. However, a set of functional test data is still needed to validate the functional path portions of the interface connections that bypass the boundary scan registers. This set of functional test data must be created manually, with all of the disadvantages discussed above. Additionally, the set of boundary scan registers takes up space on the reconfigurable device that could otherwise be devoted to different features.
It is therefore desirable for a system and method of testing interface connections between IP cores and functional blocks on a reconfigurable device enable complete testing without the need for manually-created sets of functional test data. It is further desirable that a system and method of testing interface connection does not require additional devices, such as boundary scan registers, to be included in the reconfigurable device.